As nanometer technology nodes advance more and more into the deep sub-micron regimes, static random access memory (SRAM) design must face increasingly stringent requirements. As the devices are scaled down, the supply voltage must also be scaled lower to reduce power consumption. The successful design of SRAMs with the resulting minimum-size transistors at the reduced power supply voltages is quite challenging. For example, write failure becomes an issue in such highly-scaled memories. In a write failure, the write operation is unsuccessful at flipping the stored value in the memory cell.
Some basic SRAM operation concepts will now be discussed to better illustrate the challenges of scaling SRAM into the advanced process nodes. An SRAM memory cell comprises a pair of cross-coupled inverters. If a first one of the cross-coupled inverters is driving out a stored data value Q, that value is inverted by the remaining second cross-coupled inverter as the complementary value Q. But the second cross-coupled inverter drives Q as the input to the first cross-coupled inverter, which reinforces its Q output, which in turn reinforces the Q output of the second cross-coupled inverter. An SRAM memory cell thus latches the desired Q value into the pair of cross-coupled inverters and robustly holds this latched value.
Each cross-coupled inverter comprises a serial stack of a pull-up PMOS transistor and a pull-down NMOS transistor. The pull-up PMOS transistors are also denoted as the load transistors. Because the stacked PMOS and NMOS transistors are powered by a power supply, an SRAM cell drives out its stored memory cell value through the resulting gain in the powered transistors. In contrast, a dynamic random access memory (DRAM) memory cell has no such active drive. Instead, a DRAM memory cell has a passive capacitor for storing the memory cell value. For this reason, SRAM operation is much faster than for a comparable DRAM.
Although this cross-coupled interaction in an SRAM memory cell is one of its strengths, it also becomes a problem in the advanced process nodes. For example, an SRAM memory cell is accessed in a read or write operation through a pair of NMOS access transistors. These NMOS access transistors cannot be too strong compared to the pull-up PMOS transistors or a read operation would destroy the stored memory cell value. In advanced process nodes, however, the pull-up PMOS transistors become too strong as compared to the NMOS access transistors. The write operation can thus fail to flip the stored memory cell value at advanced process nodes.
Several techniques have been developed to address this write failure. For example, the supply voltage to an SRAM memory cell may be lowered during a write operation to the SRAM memory cell. The lowered supply voltage weakens the pull-up PMOS transistors so that the write operation may invert (if necessary) the binary state of the stored memory cell value. Although this write-assist technique is successful to address write failure, the write frequency suffers because the memory cell supply voltage must recover to its default value after completion of the write-assisted write operation.
Accordingly, there is a need in the art for improved write-assisted memories having faster operation speeds.